Increment the state variable value at three different sections of the code, which will definitely iterate once in a one-loop scan. In a single-thread design, we can use state-machine-like architecture as shown in the code snippet below. The traditional approach for a single-thread design is to kick WDT at the end of the main loop. 3: Traditional watchdog Timer kicking inside the main loop Implementation of watchdog timer for single-thread software design Fig. If the system is not time-critical, it is better to choose time-out in seconds. Very short time-out periods may lead to the system resetting unnecessarily. The initialisation after a watchdog reset should be much shorter than power-on initialisation. For example, in case of a pacemaker machine, the system must boot-up almost within a heartbeat. After watchdog reset, the system must boot-up as fast as possible. In such a system, time-out period needs to be very precise. The design with delays in various places in the code has control of the watchdog, which can prove to be problematic.įor some time, critical application and recovery time from the watchdog reset is very important. A software delay routine will also increase loop latency. An unusual number of interrupts may happen during a single scanning of a loop, and the extra time spent in the interrupt service routine (ISR) will increase the main loop latency. Watchdog time-out periodįor selecting watchdog time-out period, we must have a proper understanding of the software loop latency. To get optimum benefit, implementation of the watchdog is a must for robust design. Simply enabling WDT and kicking it regularly is not enough to ensure system reliability.
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